TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 245

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

There is no dataphase
There is dataphase
bmRequestType
bmRequestType
010000xxB
010000xxB
(b) Control write/request
bmRequestType, bRequest, wValue, wIndex, wLength registers,and process
each request. According to application, access Setup_Received register after
request has been identified. UDC must also be informed that the INT_SETUP
interrupt has been recognized. If application processing is finished, write “0”
to EP0 bit of EOP register. When UDC receives this, the status stage finishes
automatically.
confirm EP0_DSET is “1”. After confirming, read data FIFO of endpoint 0. If
data is more than payload, write data after it confirming whether the
EP0_DSET_A bit in DATASET register is “1”. (INT_ENDPOINT0 interrupt
can be used.) If reading all data is finished, write “0” to EP0 bit of EOP
register. When UDC receives this, the status stage finishes automatically.
normally. If finishing status stage normally is recognized by external
application, manage this stage by using this interrupt signal. If status stage
cannot be finished normally and during status stage, a new SETUP token may
be received. In this case, when INT_SETUP interrupt signal is asserted, “1” is
set to STAGE_ERROR bit of EP0_STATUS registerinforming externally that
the status stage cannot be finished normally.
bmRequestType, bRequest, wValue, wIndex, wLength registers, and process
each request. According to application, access Setup_Received register after
request has been identified. UDC must also be informed that the INT_SETUP
interrupt has been recognized.
When
After receiving data prepared in application, access DATASET register, and
INT_STATUS interrupt is asserted when UDC finishes status stage
Vendor specific
Vendor specific
When INT_SETUP is received, identify contents of device request by
bRequest
bRequest
INT_SETUP is received,
Vendor specific
Vendor specific
92CH21-243
wValue
wValue
Vendor specific
Vendor specific
wIndex
wIndex
identify
Vendor specific
(Except for 0)
wLength
wLength
contents
0
of request
TMP92CH21
Vendor data
2009-06-19
Data
None
Data
by