TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 38

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

♦: After clearing the HALT mode, CPU starts interrupt processing.
○
×: Cannot be used to release the HALT mode.
−: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
*1: Release of the HALT mode is executed after warm-up time has elapsed.
*2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the
Status of Received Interrupt
: After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT
Shift to IDLE1 mode :
Release from IDLE1 mode :
construction of low power dissipation systems. However, the method of use is limited as below.
instruction.
level. This combination is not available.
INTWD
INT0 to INT4 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3,
INTTB0 to INTTB1
INTRX0 to INTRX1,
TX0 to TX1
INTTBO0, INTI2S
INTAD, INT5
INTKEY
INTRTC
INTUSB
INTLCD
RESET
HALT Mode
Example: Releasing IDLE1 mode
Address
8200H
8203H
8206H
8209H
820BH
820EH
820FH
Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation
INT0
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request)
Release Halt state by INT_URST_STR or INT_URST_END request (RESET request)
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
LD
LD
LD
EI
LD
HALT
LD
5
XX, XX
(PCFC), 01H
(SYSCR2), 28H
(IIMC), 00H
(INTE0AD), 06H
IDLE2
(
Interrupt level) ≥ (Interrupt mask)
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Interrupt Enabled
92CH21-36
IDLE1
♦* 2
♦
♦
♦
♦
×
×
×
×
×
×
;
;
;
;
;
;
Sets PC0 to INT0.
Selects INT0 interrupt rising edge.
Sets INT0 interrupt level to 6.
Sets interrupt level to 5 for CPU.
Sets HALT mode to IDLE1 mode.
Halts CPU.
STOP
♦* 1
♦* 1
♦* 1
×
×
×
×
×
×
×
×
Initialize LSI
(
Interrupt level) < (Interrupt mask)
IDLE2
○
○
○
○
○
−
×
×
×
×
×
Interrupt Disabled
INT0 interrupt routine
RETI
IDLE1
○
○
○
○
○
−
×
×
×
×
×
* 2
TMP92CH21
2009-06-19
STOP
○
○
○
−
×
×
×
×
×
×
×
* 1
* 1
* 1