TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 261

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.10.7 The Control Flow in UDC (Control Write Transfer Type)
correspond with the data number specified by the device request. The CPU can
therefore process using INT_STATUSNAK interrupt. However, when class and
vendor request is used, wLength value corresponds to data transfer number in
data phase. With this setting, using this interrupt is not need. Data stage data
can be confirmed by accessing DATASIZE register.
OUT
Stage change condition of control writes transfer type
These changing conditions are shown in Figure 3.10.7.
In control read transfer type, transaction number of data stage does not always
1.
2.
3.
DATA1
Receive SETUP token from host.
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•
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Receive OUT token from host.
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•
•
•
•
•
•
Receive IN token from host.
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•
Setup Received register
Start setup stage in the UDC.
Receive data in request normally and judge. And assert INT_SETUP
interrupt externally.
Change data stage in the UDC.
CPU receives a request from the request register every INT_SETUP
interrupt.
Judge request and access Setup Received register for inform the UDC
that INT_SETUP interrupt has been recognized.
Receive dataphase data normally, and set EP0 bit of DATASET
register.
The CPU receives data in FIFO by setting DATASET.
The CPU processes receiving data by device request.
When the CPU finishes transaction, it writes “0” to EP0 bit of EOP
register.
Change status stage in the UDC.
Return data packet of 0 data to IN token and change state to IDLE in
the UDC.
Assert INT_STATUS interrupt externally when ACK for 0 data
packet is received.
ACK
OUT
92CH21-259
DATA0
NAK
EP0_FIFO (RD of payload)
OUT
DATA0
EP0_FIFO (Rest data)
ACK
IN
NAK
IN
TMP92CH21
EOP register
2009-06-19
DATA1
ACK