TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 44

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.4
Interrupts
status register) and by the built-in interrupt controller.
Non-maskable interrupts have a fixed priority level of 7, the highest level.
to the CPU. When more than one interrupt is generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority level is 7, the level used for non-maskable interrupts.)
CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU accepts the interrupt.
processed irrespective of the value in <IFF2:0>.
(EI num sets <IFF2:0> to num). For example, the command EI 3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all
non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence
both are equivalent to the command EI 1).
instruction is used to disable all maskable interrupts (since the priority level for maskable
interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed.
micro DMA processing mode.
blocks; this mode allows high-speed data transfer to and from internal and external memory
and internal I/O ports.
processing is requested in software rather than by an interrupt.
Interrupts are controlled by the CPU Interrupt mask register <IFF2:0> (bits12 to 14 of the
The TMP92CH21 has a total of 50 interrupts divided into the following five types:
A fixed individual interrupt vector number is assigned to each interrupt source.
Any one of six levels of priority can also be assigned to each maskable interrupt.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
The CPU compares the interrupt priority level which it receives with the value held in the
However, software interrupts and illegal instruction interrupts generated by the CPU are
The value in the interrupt mask register <IFF2:0> can be changed using the EI instruction
The DI instruction (sets <IFF2:0> to 7) is exactly equivalent to the EI 7 instruction. The DI
In addition to the general purpose interrupt processing mode described above, there is also a
In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte
In addition, the TMP92CH21 also has a software start function in which micro DMA
Figure 3.4.1 is a flowchart showing overall interrupt processing.
Interrupts generated by CPU: 9 sources
Internal interrupts: 34 sources
External interrupts: 7 sources
Software interrupts: 8 sources
Illegal instruction interrupt: 1 source
Internal I/O interrupts: 26 sources
Micro DMA transfer end interrupts: 8 sources
Interrupts on external pins (INT0 to INT5, INTKEY)
92CH21-42
TMP92CH21
2009-06-19