TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 125

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(2) Note on NAND flash area setting
3FFFFFH, the following explanation is given.
be accessed at the same time and a problem such as data conflict will occur.
Kbytes of address 000000H to 007FFFH as the
setting.
Note: In this case, the 32 Kbytes of address 000000H to 007FFFH in CS3’s memory
Figure 3.6.5 shows a memory map for a NAND flash and RAM built-in LCD driver.
Ssince it is recommended that CS3 area be assigned to the address 000000H to
In this case, the NAND flash and RAM built-in LCD driver overlap with CS3 area.
However, each access control circuit in the TMP92CH21 operates independently.
So, if a program on CS3 area accesses NAND flash, both
To avoid this phenomenon, it is recommended that CS0 area be assigned to the 32
Since CS0 has priority over CS3, only NAND flash will be accessed correctly by this
cannot be used.
Figure 3.6.5 Recommended CS3 and CS0 Setting
001D00H
001FE0H
001F00H
001FF0H
000000H
002000H
006000H
008000H
200000H
400000H
RAM built-in LCDD (16 bytes)
92CH21-123
(
Internal RAM
COMMON X
NAND flash
Not assigned
(16 Kbytes)
Internal I/O
(512 bytes)
(2 Mbytes)
(2 Mbytes)
LOCAL X
)
CS0
pin will not be needed.
CS3 area setting 000000H to
3FFFFFH (4 Mbytes)
CS3
and NAND flash will
CS0 area setting 000000H to
007FFFH (32 Kbytes)
TMP92CH21
2009-06-19