TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 342

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.3
3.14.3.1 Description of Operation
Shift Register Type LCD Driver Control Mode (SR mode and STN color)
and LCD size to control registers before setting start register.
reads data from source memory. After data reading from source data is completed, the
LCDC cancels the bus release request and the CPU will restart. The LCDC then
transmits LCD size data to the external LCD driver through the LD bus (special data
bus only for LCD driver). At this time, the control signals (LCP0 etc.) connected to the
LCD driver output the specified waveform which is synchronized with the data
transmission.
LCDSCC. LCDSCC is the base clock for the LCD controller, which is generated by
system clock f
rate can be set using this special generator. This generator is made from an 8-bit
counter and 1/16 speed clock from the system clock.
Note 1: During data read from source memory (during DMA operation), the CPU is
Note 2: This LSI has a 16-Kbyte SRAM, this internal RAM is available for use as display
(16 grayscales), 8 bpp (256 colors) and 12 bpp (4096 colors). Display RAM is supported
by external SDRAM, SRAM and internal RAM (16 Kbytes).
between pixels in panels. Special adjustment is not required.
colors. Support is also given for 4096 colors out of a pallet of 4096 colors.
selectable between 2 modes.
Set the mode of operation, start address of source data save memory, grayscale level
After setting start register, the LCDC outputs a bus release request to the CPU and
The LCD controller generates control signals (LFR, LBCD, LLP etc.) from base clock
This LSI has a special clock generator for the LCDC. Details of LCD frame refresh
This LCDC supports monochrome, 2 bpp (4 grayscales), 3 bpp (8 grayscales), 4 bpp
It is automatically set to suitable condition data correction against interference
In passive matrix STN mode, 8 bpp (256 colors) is supported out of a palette of 4096
Data output width is selectable between 4 bits or 8 bits, and data output sequence
SR type LCD control setting is described below.
stopped by the internal BUSREQ signal. When using SR mode LCDC,
programmers must monitor CPU performance.
RAM. Internal RAM access is very fast (32-bit bus width, 1 SYSCLK read/write), it
is possible to reduce CPU load to a minimum, enabling LCDC DMA.
SYS
.
92CH21-340
TMP92CH21
2009-06-19