TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 472

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
Note: The phase relation between X1 input signal and the other signals is undefined.
D0~D31
A0~A23
(1) Read cycle (0 waits)
SDCLK
SRWR
SRxxB
The above timing chart is an example.
WAIT
R/
CSn
RD
X1
W
t
OSC
t
RRH
t
t
CH
AR
t
CYC
t
t
RK
92CH21-470
t
AD
CL
t
SBA
t
TK
t
KT
t
t
RR
RD
Data input
t
t
HA
HR
TMP92CH21
2009-06-19

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