TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 314

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers
(5) AD conversion time
(6) Storing and reading the results of AD conversion
channel.
store the results of AD conversion. (ADREG0H/L to ADREG3H/L are read-only
registers.)
successively in registers ADREG0H/L to ADREG3H/L. In other modes the AN0, AN1,
AN2, AN3 and AN4 conversion results are stored in ADREG0H/L, ADREG1H/L,
ADREG2H/L and ADREG3H/L respectively.
registers which are used to hold the results of AD conversion.
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion result
registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
ADMOD0<EOCF> to 0.
Analog Input Channel
132 states (6.6 μs at f
The AD conversion data upper and lower registers (ADREG0H/L to ADREG3H/L)
In channel fixed repeat conversion mode, the conversion results are stored
Table 3.11.3 shows the correspondence between the analog input channels and the
<ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD
Reading the AD conversion result also clears the AD conversion end flag
(Port G)
AN0
AN1
AN2
AN3
Other than at Right
Conversion Modes
SYS
92CH21-312
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
= 20 MHz) are required for the AD conversion of one
AD Conversion Result Register
(ADMOD0<ITM0 = 1>)
Channel Fixed Repeat
Conversion Mode
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
TMP92CH21
2009-06-19