TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 200

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

USBINTFR2
USBINTFR3
(07F1H)
(07F2H)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
Note: The EPx_FULL_A/B and EPx_Empty_A/B flags are not status flags. Therefore, check DATASET register to
When read
When write 0: Clear flag
determine if FIFO-status is needed.
EP1_FULL_A
EP3_FULL_A
R/W
R/W
7
0
7
0
•
•
EPx_FULL_A/B:
EPx_Empty_A/B:
1:
1:Generate
0:Not generate
(When transmitting)
(When receiving)
(When transmitting)
(When receiving)
−
EP1_Empty_A
EP3_Empty_A
This is set to “1” when CPU full writes data to FIFO_A/B.
This is set to “1” when UDC full receives data to FIFO_A/B.
This is set to “1” when FIFO becomes empty after transmission.
This is set to “1” when FIFO becomes empty after CPU reads all data from FIFO.
interrupt
interrupt
R/W
R/W
When read 0: Not generate interrupt
6
0
6
0
EP1_FULL_B
R/W
1: Generate interrupt
5
0
5
92CH21-198
EP1_Empty_B
R/W
4
0
4
EP2_FULL_A
R/W
When write 0: Clear flag
3
0
3
EP2_Empty_A
R/W
1: −
2
0
2
EP2_FULL_B
R/W
1
0
1
TMP92CH21
2009-06-19
EP2_Empty_B
R/W
0
0
0