TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 124

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.6.6
Cautions
(1) Note on timing between
(Chip select signal), it is possible that an unintended read cycle occurs due to a delay in
the read signal. Such an unintended read cycle may cause a problem, as in the case of
(a) in Figure 3.6.3.
the toggle bit correctly since it always reads same value for the toggle bit. To avoid this
phenomenon, data polling function control is recommended.
Example: When using an externally connected NOR flash which uses JEDEC standard
If the parasitic capacitance of the
When the toggle bit is reversed by this unexpected read cycle, the CPU cannot read
SDCLK
(20 MHz)
A23 to A0
CSm
CSn
RD
Figure 3.6.4 NOR Flash Toggle Bit Read Cycle
commands, note that the toggle bit may not be read out correctly. If the read
signal in the cycle immediately preceding the access to the NOR flash does not
go high in time, as shown in Figure 3.6.4, an unintended read cycle like the one
shown in (b) may occur.
Figure 3.6.3 Read Signal Delay Read Cycle
chip select
NOR flash
A23 to A0
Toggle bit
(20 MHz)
SDCLK
RD
Memory access
CS
92CH21-122
and
RD
RD
(b)
(Read signal) is greater than that of the
Toggle bit RD cycle
(a)
TMP92CH21
2009-06-19
CS