TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 209

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Endpoint0
Endpoint1
Endpoint2
Endpoint3
(0780H)
(0781H)
(0782H)
(0783H)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.10.3.2 EPx_FIFO Register (x: 0 to 3)
Note1: Read or write to these window registers using 1-byte load instructions only, since each register has only a
Note2: When it is IN-token(except isochronous transfer) and the UDC transmits 1-byte data to the host, if the CPU
1-byte address. Do not use load instructions of 2 bytes or 4 bytes.
writes “eop” to the endpoint on a certain timing, a NULL data(0-byte data) may be transmitted.Therefore,
prevent the tramsfer of 1-byte by for example introducing dummy data.
EP0_DATA7
EP1_DATA7
EP2_DATA7
EP3_DATA7
defined by the endpoint descriptor, for each endpoint automatically. By this means,
each endpoint is automatically set to each direction.
8-byte registers:
wLength_L and wLength_H. These are updated whenever a new SETUP token is
received from the host.
the new device request has been received.
the request received.
the
STANDARD_REQUEST_FLAG and REQUEST_FLAG.
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
This register is prepared for each endpoint independently.
This is the window register from or to FIFO RAM.
In the auto bus enumeration, the request controller in UDC sets the mode, which is
The device request that is received from the USB host is stored in the following
bmRequestType,
When the UDC receives without error, INT_SETUP interrupt is asserted, meaning
There is also a request which is operated automatically by the UDC, depending on
In that case, the UDC does not assert the INT_SETUP interrupt. Any request which
7
7
7
7
UDC
EP0_DATA6
EP1_DATA6
EP2_DATA6
EP3_DATA6
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
6
6
6
6
is
currently
EP0_DATA5
EP1_DATA5
EP2_DATA5
EP3_DATA5
bRequest,
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
5
5
5
5
92CH21-207
EP0_DATA4
EP1_DATA4
EP2_DATA4
EP3_DATA4
Undefined
Undefined
Undefined
Undefined
operating
wValue_L,
R/W
R/W
R/W
R/W
4
4
4
4
EP0_DATA3
EP1_DATA3
EP2_DATA3
EP3_DATA3
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
3
3
3
3
can
wValue_H,
EP0_DATA2
EP1_DATA2
EP2_DATA2
EP3_DATA2
be
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
2
2
2
2
checked
wIndex_L,
EP0_DATA1
EP1_DATA1
EP2_DATA1
EP3_DATA1
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
1
1
1
1
TMP92CH21
by
2009-06-19
wIndex_H,
EP0_DATA0
EP1_DATA0
EP2_DATA0
EP3_DATA0
Undefined
Undefined
Undefined
Undefined
reading
R/W
R/W
R/W
R/W
0
0
0
0