TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 260

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.10.6 The Control Flow in UDC (Control Read Transfer Type)
Stage change condition of control read transfer type
These changing conditions are shown in Figure 3.10.6.
1.
2.
3.
IN
Receive SETUP token from host
•
•
•
Receive IN token from host
•
•
•
•
•
•
•
Receive OUT token from host.
•
•
NAK
Setup Received register
Start setup stage in UDC.
Receive data in request normally and judge. And assert INT_SETUP
interrupt externally.
Change data stage in the UDC.
The CPU receives a request from the request register every
INT_SETUP interrupt.
Judge request and access Setup Received register to inform the UDC
that INT_SETUP interrupt has been recognized .
According to Device request, monitor EP0 bit of DATASET register,
and write data to FIFO.
If the UDC is set data of payload to FIFO or CPU set short packet
transfer in EOP register, EP0 bit of DATASET register is set.
The UDC transfers data that is set to FIFO to host by IN token
interrupts.
When the CPU finishes transaction, it writes “0” to EP0 bit of EOP
register.
Change status stage in the UDC.
Return ACK to OUT token and change state to IDLE in the UDC.
Assert INT_STATUS interrupt externally.
IN
92CH21-258
DATA1
ACK
EP0_FIFO (WR of payload)
EP0_FIFO (Rest data)
IN
DATA0
ACK
OUT
EOP register
DATA1
TMP92CH21
2009-06-19
ACK