TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 427

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

TSICR0
(01F0H)
TSICR1
(01F1H)
3.19.2
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
PXD (Internal Pull-down resistance) ON/OFF setting
<TSI7>
Note1:
Note2: Ex:
Touch Screen Interface (TSI) Control Register
<PXEN>
0
1
Since an internal clock is used for the debounce circuit, when IDLE1, STOP mode, the de-bounce circuit
don’t operate and also interrupt which through this circuit is not generated. When IDLE1, STOP mode, set
this circuit to disable (Write “0” to TSICR1<DBC7>) before entering HALT state.
TSICR1=95H →N = 64 + 4 + 1 = 69
0: Disable
1: Enable
0: Disable
1: Enable
DBC7
TSI7
OFF
R/W
R/W
ON
7
0
7
0
0
DB1024
1024
R/W
6
6
0
OFF
OFF
Debounce Time Setting Register
1
“N” is the number of bits between bit6 and bit0 which are set to “1”. Note2)
Detection
condition
0: no touch
1: touch
TSI Control Register
DB256
PTST
R/W
256
Debounce time is set by the formula “(N × 64 − 16)/f
92CH21-425
5
R
5
0
0
INT4
interrupt
control
0: Disable
1: Enable
TWIEN
DB64
R/W
R/W
64
4
4
0
0
SPY
0 : OFF
1 : ON
PYEN
R/W
DB8
R/W
3
3
0
0
8
SPX
0 : OFF
1 : ON
PXEN
R/W
DB4
R/W
2
2
0
0
4
SMY
0 : OFF
1 : ON
SYS
MYEN
DB2
R/W
R/W
1
1
0
0
2
”.
TMP92CH21
2009-06-19
SMX
0 : OFF
1 : ON
MXEN
R/W
DB1
R/W
0
0
0
0
1