TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 112

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Bit symbol
Specified value
Bit symbol
Specified value
Bit
Bit
(iii) Example of register setting
M1V21
M1S23
7
0
Note 1: When the set block address area overlaps with the built-in memory area, or
Note 2: If an address area other than
7
as follows.
0
with address A23 to A16.
value, the start address of the block address area is set to address 110000H.
are set whether addresses A21 to A16 and A8 are compared or not. In register
setting, “0” is “compare”, and “1” is “do not compare”. M1V15 to M1V9 bits
determine whether addresses A15 to A9 are compared or not with bit 1. A23 and
A22 are always compared.
start addresses. Therefore, 512 bytes (addresses 110000H to 1101FFH) are set as
block address area 1, and if it is compared with the addresses on the bus, the chip
select signal CS1 is set to “low”.
A8 are compared or not is determined by the register.
to A15 are compared or not is determined by the register.
To set the block address area 64 Kbytes from address 110000H, set the register
M1S23 to M1S16 bits of the memory start address register MSAR1 correspond
A15 to A0 are set to “0”. Therefore, if MSAR1 is set to the above mentioned
M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1
When set as above, A23 to A9 are compared with the value that is set as the
The other block address area sizes are specified in the same way.
A23 and A22 are always compared with block address area 0. Whether A20 to
Similarly, A23 is always compared with block address areas 2 to 5. Whether A22
both two address areas overlap, the block address area is processed
according to priority as follows.
as
setting of
M1V20
M1S22
Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3
6
0
6
0
CSEX
. Therefore, wait number and data bus width controls follow the
CSEX
M1V19
M1S21
5
0
5
0
MAMR1 Register
MSAR1 Register
92CH21-110
(BEXCSH, BEXCSL register).
M1V18
M1S20
4
0
4
1
CS
0
M1V17
M1S19
to
3
0
3
0
CS
3
is accessed, this area is regarded
M1V16
M1S18
2
0
2
0
M1V15 to M1V9
M1S17
1
0
1
0
TMP92CH21
2009-06-19
M1S16
M1V8
0
1
0
1