TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 353

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.3.6 LCD Data Transmission Speed and Data Bus Occupation Rate
Note: When using SDRAM for display RAM, overhead time (+ 8 clocks) is required for
Note: For t
External SDRAM
Display RAM
External SRAM
Internal RAM
and reads data from source memory. The LCDC then transmits LCD size data to
the external LCD driver through the special LCDC data bus (LD11 to LD0). At
this time, the control signals connected to the LCD driver output the specified
waveform which is synchronized with the data transmission. After data reading
from RAM for display is completed, the LCDC cancels the bus release request and
the CPU will restart.
stopped by the internal BUSREQ signal. When using SR mode LCDC,
programmers must monitor CPU performance. The occupation rate of the data
bus depends on data size, transmission speed (CPU clock speed) and display RAM
type used.
is calculated by the equation below for each display mode.
When SDRAM is used, more overhead time is required.
After setting start register, the LCDC outputs a bus release request to the CPU
During data read from source memory (during DMA operation), the CPU is
t
Data bus occupation rate equals the percentage of t
every 1 row data reading.
STOP
Data bus occupation rate = t
t
t
SegNum
K
STOP
STOP
LP
refers to the CPU stoppage time during transmission of 1 row data. t
time, refer to “refresh rate setting”.
= (SegNum × K/8) × t
= (SegNum × K/8) × t
: bit number per pixel (bpp)
: Number of segment
Bus Width
Monochrome
4 Grayscales
8/16 Grayscales
256 colors
4096 colors
16 bits
32 bits
32 bits
16 bits
32 bits
92CH21-351
LRD
LRD
Valid Data Reading Time
STOP
+ ((1/f
(f
SYS
K = 1
K = 2
K = 4
K = 8
K = 12
/t
SYS
LP
) × 8)
Clock/Byte)
*1/2
*1/4
2/2
2/4
1/4
; Except SDRAM use
; SDRAM use
STOP
Valid Data Reading Time
time in t
at f
t
LRD
SYS
(ns/Byte)
*25
*12.5
50
25
12.5
= 20 MHz
TMP92CH21
LP
2009-06-19
time.
STOP