TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 499

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
PG
PM
PA
PC
PF
PK
P1
P2
P3
P4
P5
P6
P7
P8
P9
PJ
PL
(1) I/O ports (1/7)
Name
Port G
Port M
Port A
Port C
Port F
Port K
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port J
Port L
Address
000CH
001CH
003CH
004CH
0004H
0008H
0010H
0014H
0018H
0020H
0024H
0028H
0030H
0040H
0050H
0054H
0058H
register is set to “1”)
Data from external
port (Output latch
PA7
PC7
PF7
R/W
P17
P27
P37
P47
P57
P67
P87
P97
PJ7
PL7
7
0
0
1
1
1
external port
(Output latch register is set to “0”)
Data from
R/W
R
Data from external port
(Output latch register
register is set to “1”)
Data from external
port (Output latch
PA6
PC6
PL6
P16
P26
P36
P46
P56
P66
P76
P86
P96
PJ6
Data from external port (Output latch register is cleared to “0”)
Data from external port (Output latch register is cleared to “0”)
Data from external port (Output latch register is cleared to “0”)
Data from external port (Output latch register is cleared to “0”)
6
0
0
1
external port
is set to “1”)
Data from
92CH21-497
PA5
P15
P25
P35
P45
P55
P65
P75
P85
P95
PL5
PJ5
5
0
0
1
0
Data from external port
Data from external port (Output latch register is set to “1”)
PA4
P14
P24
P34
P44
P54
P64
P74
P84
P94
PJ4
PL4
4
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
PA3
PC3
PG3
PK3
P13
P23
P33
P43
P53
P63
P73
P83
P93
PJ3
PL3
R/W
0
3
0
0
1
1
0
0
(Output latch register is set to “1”)
Data from external port
(Output latch register is
Data from external port
Data from external port
(Output latch register is set to “1”)
PM2
PA2
PC2
PG2
PK2
P12
P22
P32
P42
P52
P62
P72
P82
P92
PF2
PJ2
PL2
0/1
2
0
0
1
0
0
1
Data from external port
set to “1”)
R/W
R/W
R/W
R/W
R
PM1
PA1
PC1
PG1
PK1
P11
P21
P31
P41
P51
P61
P71
P81
P91
PF1
R/W
PJ1
PL1
1
0
0
1
1
0
0
1
TMP92CH21
2009-06-19
PC0
PG0
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0
PF0
PK0
PL0
PJ0
0
0
0
1
1
1
0
0