TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 330

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(2) Writing clock data
Please use the following method to ensure data is written correctly.
When a carry over occurs during a write operation, the data cannot be written correctly.
1. Using 1Hz interrupt
2. Resetting a counter
can write correctly if writing data after 1Hz interrupt occurred.
32,768 kHz. The data is written after reset this counter.
setting time, first writing only. Therefore, if setting the clock counter correctly,
after clearing the counter, set the 1Hz-interrupt to enable. And set the time after
the first interrupt (occurs at 0.5s) is occurred.
1Hz interrupt and the count up of internal data synchronize. Therefore, data
There are 15-stage counter inside the RTC, which generate a 1Hz clock from
However, if clearing the counter, it is counted up only first writing at half of the
Figure 3.13.3 Flowchart of data write
RESTR<RSTTMR> = “1”
RESTR<DIS1HZ> = “0”
PAGER<PAGE> = “0” ,
92CH21-328
First interrupts occur
enable 1Hz interrupt
Select PAGE0
Sets the time
reset counter
(After 0.5s)
Start
END
YES
NO
TMP92CH21
2009-06-19