TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 438

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Write to FIFO
<TXE>
I2SCKO pin
I2SDO pin
<BUSY>
INTI2S
I2SCKO pin
I2SDO pin
(3) Notes
1)
2)
3)
4)
1
INTI2S timing
I2SCTL0 <TXE>
stopped by programming “0”.
immediately.
FIFO size
please use even numbers (2, 4 ... 32).
automatically after transmitting all programmed data to FIFO. In case of
continuous transmitting, program “1” to <TXE> after programming data to FIFO.
programming “1” to <TXE>.
Address for I2SBUFR and I2SBUFL
word data load instruction”. A “byte data load instruction” cannot be used.
10 MHz
LSB
Bit0
INTI2S is generated after the last data of FIFO is loaded to the internal shifter.
FIFO is now empty and it is possible to write the next data.
A transmission is started by programming “1” to the <TXE> register and
<TXE> register is cleared to “0” when <BUSY> changes from “1” to “0”.
When <TXE> is programmed “0” during transmitting, transmitting stops
A 32-byte FIFO is provided for SIO mode. It is not necessary to use all data but
The <BUSY> will be changed to “0” and <TXE> will be cleared to “0”
The number of data programmed to FIFO is counted automatically and held by
If writing data to I2SBUFR (I2SBUFL cannot be written), use “word or long
The address of I2SBUFR is selectable from 0800H to 0803H.
2
Bit1
MSB
Bit7
Figure 3.20.7 Whole
Figure 3.20.8 Detail Timing
LSB
Bit0
92CH21-436
Bit1
31
MSB
Bit7
Timing
32
1
2
TMP92CH21
2009-06-19