TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 35

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(4) Runaway prevention using SFR protection register
(Purpose)
(Operation explanation)
(Double key)
protected from runaway caused by stopping of the clock or by changes to the
memory control register (memory controller, MMU)
operations.
possible by setting up a double key to EMCCR1 and EMCCR2 registers.
executed with protection in the ON state.
Prevention of program runaway caused by introduction of noise.
Write operations to a specified SFR are prohibited so that the program is
Runaway error handling is also facilitated by INTP0 interruption.
Specified SFR list
Execute and release of protection (write operation to specified SFR) becomes
1st KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2
2nd KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2
Protection state can be confirmed by reading EMCCR0<PROTECT>.
At reset, protection becomes OFF.
INTP0 interruption also occurs when a write operation to the specified SFR is
1. Memory controller
2. MMU
3. Clock gear
4. PLL
B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR,
BROMCR
LOCALPX/PY/PZ, LOCALLX/LY/LZ,
LOCALRX/RY/RZ, LOCALWX/WY/WZ,
SYSCR0, SYSCR1, SYSCR2, EMCCR0
PLLCR0, PLLCR1
92CH21-33
which prevent fetch
TMP92CH21
2009-06-19