TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 113

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(2) Connection memory specification
(3) Data bus width specification
type that is connected with the block address areas. The interface signal is outputted
according to the set memory as follows.
the control register (BnCSH)<BnBUS1:0> as follows.
called “dynamic bus sizing”. The part of the data bus to which the data is output
depends on the data size, baus width and start address.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories
Setting the <BnOM1:0> bit of the control register (BnCSH) specifies the memory
The data bus width is set for every block address area. The bus size is set by setting
This method of changing the data bus width depending on the accessing address is
Note: SDRAM should be set to either “01” (16-bit bus) or “10” (32-bit bus).
Note 1: SDRAM should be set to block either 1 or 2.
Note 2: Set “00” for NAND flash, RAM built-in LCDD.
<BnOM1>
with different bus width are put in consecutive addresses, do not execute an
access to both memories with one command.
BnBUS 1
0
0
1
1
0
0
1
1
<BnOM1: 0> Bit (BnCSH Register)
<BnBUS1:0> bit (BnCSH Register)
<BnOM0>
BnBUS 0
0
1
0
1
0
1
0
1
92CH21-111
SRAM/ROM (Default)
(Reserved)
(Reserved)
SDRAM
8-bit bus mode (Default)
16-bit bus mode
32-bit bus mode
Don’t use this setting
Function
Function
TMP92CH21
2009-06-19