TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 524

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

TB0FFCR
TB0RG0H
TB0RG1H
TB0CP0H
TB0CP1H
TB0RG0L
TB0RG1L
TB0CP0L
TB0CP1L
Symbol
TB0MOD
TB0RUN
(10) 16-bit timer
16-bit timer
16-bit timer
16-bit timer
16-bit timer
register 0
register 0
register 1
register 1
register 0
register 0
register 1
register 1
Capture
Capture
Capture
Capture
Name
TMRB0
register
TMRB0
register
TMRB0
register
flip-flop
control
mode
RUN
high
high
high
high
low
low
low
low
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
118CH
118DH
118AH
118BH
118EH
118FH
1180H
1182H
RMW)
1183H
RMW)
1188H
RMW)
1189H
RMW)
RMW)
RMW)
Double
buffer
0: Disable
1: Enable
Always write “0”.
Always write “11”.
TB0RDE
R/W
7
0
−
0
−
1
R/W
W*
Always
write “0”
R/W
6
−
0
−
0
−
1
92CH21-522
Invert when
the UC value
is loaded in
to
TB0CP1H/L.
Execute
0: capture
1:
TB0FF0 inversion trigger
0: Disable trigger
1: Enable trigger
software
capture
TB0CP0I TB0CPM1 TB0CPM0
TB0CT1
Undefined
W*
5
1
0
Invert when
the UC value
is loaded in
to
TB0CP0H/L.
Capture timing
00: Disable
01: Reserved
10: Reserved
11: TA1OUT↑
TB0C0T1
TA1OUT↓
4
0
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
W
W
W
W
R
R
R
R
−
−
−
−
−
−
−
−
Invert when
the UC value
matches the
value in
TB0RG1H/L
IDLE2
0: Stop
1: Operate
TB0E1T1
I2TB0
R/W
R/W
3
0
0
0
Invert when
the UC value
matches the
value in
TB0RG0H/L
TB0PRUN
TMRB0
prescaler
0: Stop and clear
1: Run (Count up)
Control
up counter
0: Disable
1: Enable
TB0E0T1 TB0FF0C1 TB0FF0C0
TB0CLE
clearing
clearing
R/W
R/W
2
0
0
0
TMRB0 source clock
00: Reserved
01: φT1
10: φT4
11: φT16
Control TB0FF0
00: Invert
01: Set
10: Clear
11: Don’t care
* Always read as “11”
TB0CLK1 TB0CLK0
1
0
1
TMP92CH21
2009-06-19
W*
UP counter
(UC10)
TB0RUN
R/W
0
0
0
1