TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 166

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Note: Transfer rates in I/O interface mode are eight times faster than the values given above.
f
SYS
12.2880
14.7456
19.6608
22.1184
24.5760
9.8304
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
[MHz]
trigger of timer
Method for calculating the timer output frequency which is needed when outputting
TA0TRG frequency = Baud rate × 16
(when baud rate generator is used and BR0CR<BR0ADDE> = 0)
Note: The TMRA0 match detect signal cannot be used as the transfer clock in I/O
transfer clock.
Frequency Divider
In UART mode, TMRA match detect signal (TA0TRG) can be used for serial
Interface mode.
Table 3.9.3 Selection of Transfer Rate (1)
10
10
10
A
C
A
2
4
8
5
2
3
6
1
2
4
8
3
1
2
4
5
8
Input Clock
92CH21-164
(f
115.200
307.200
153.600
115.200
384.000
192.000
76.800
38.400
19.200
38.400
19.200
76.800
38.400
19.200
76.800
38.400
19.200
96.000
76.800
48.000
38.400
24.000
SYS
9.600
φT0
/4)
(f
SYS
19.200
28.800
19.200
76.800
38.400
19.200
28.800
96.000
48.000
24.000
19.200
12.000
9.600
4.800
2.400
9.600
4.800
9.600
4.800
9.600
4.800
9.600
6.000
φT2
/16)
(f
SYS
19.200
24.000
12.000
4.800
2.400
1.200
0.600
2.400
1.200
7.200
4.800
2.400
1.200
9.600
4.800
2.400
1.200
7.200
6.000
4.800
3.000
2.400
1.500
φT8
/64)
Unit (Kbps)
(f
SYS
φT32
1.200
0.600
0.300
0.150
0.600
0.300
1.800
1.200
0.600
0.300
4.800
2.400
1.200
0.600
0.300
1.800
6.000
3.000
1.500
1.200
0.750
0.600
0.375
TMP92CH21
/256)
2009-06-19