TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 52

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

ZZ:
Note1: N stands for the micro DMA channel number (0 to 7)
Note2: The transfer mode register should not be set to any value other than those listed above.
Note3: The execution state number shows number of best case (1-state memory access).
0
DMAMn[4:0]
1 1 1 0 0
0 0 0 z z
0 0 1 z z
0 1 0 z z
0 1 1 z z
1 0 0 z z
1 0 1 z z
1 1 0 z z
0
00 = 1-byte transfer
01 = 2-byte transfer
10 = 4-byte transfer
11 = (Reserved)
DMADn+/DMASn+: Post-increment (register value is incremented after transfer)
DMADn−/DMASn−: Post-decrement (register value is decremented after transfer)
“I/O” signifies fixed memory addresses; “memory” signifies incremented or decremented memory
addresses.
0
(4) Detailed description of the transfer mode register
Destination INC mode
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Destination DEC mode
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Source INC mode
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Source DEC mode
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Source and destination INC mode
(DMADn+) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Source and destination DEC mode
(DMADn−) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Source and destination Fixed mode
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
Mode
DMAM0 to DMAM7
Mode Description
92CH21-50
State Number
Execution
5 states
5 states
5 states
5 states
6 states
6 states
5 states
5 states
TMP92CH21
2009-06-19