TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 275

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Note: NULL packet can also be set by accessing EOP register.
(2) Interrupt control
Example:
DATASET_A
DATASET_B
EPx_EOPB
(c) Issuance of NULL packet
Interrupt signal is prepared. This function uses adept system.
For detail refer to 3.10.2 900/H1 CPU I/F.
length is set to FIFO, and NULL packet can be transferred to IN token.
level condition (where FIFO is empty). If it answers to receiving IN token by using
NULL packet in a certain period, it is answered by keeping EPx_EOPB signal to L
level.
showing space of data. Therefore, data condition (whether either has data or not)
cannot be confirmed externally.
If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0
But if NULL data is set to FIFO, it is valid only in the case where SET signal is L
However, if mode is dual packet mode, EPx_DATASET signal assert L level for
NULL
A
Neglect
92CH21-273
NULL
completion of
NULL packet
B
transmitting
NULL
A
NULL
B
NULL
A
TMP92CH21
2009-06-19