TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 84

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.5.8
Port 8 (P80 to P87)
output latches of P80 to P81, P83 to P87 to “1”.
register P8FC.
ports.
Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the
Port 8 can also be set to function as an interface pin for external memory using function
Writing “1” in the corresponding bit of P8FC and P8FC2 enables the respective functions.
Resetting <P80F> to <P87F> of P8FC to “0” and P8FC2 to “0”, sets all bits to output
Reset
AM1
P8 read
0
0
1
1
P8FC2 write
Ouptut latch
P8FC write
Function
control 2
Function
P8 write
contol
AM0
0
1
0
1
CS0
“1”,
Figure 3.5.16 Port 8
Port 82 Initial State
“1”, “1”,
,
Function Setting after Reset is Released
SDCS
CS1
92CH21-82
Selector
,
,
SDCS
CS2
CSZA
,
, “1”,
CS3
, “1”,
Don’t use this setting
,
“0” Output port
“0” Output port
“1” Output port
ND
CSZB
WRUL
0
CE
,
,
,
CSZC
ND
WRUU
1
CE
,
, “1”, “1”,
CSZD
P80 (
P81 (
P82 (
P83 (
P84 (
P85 (
P86 (
P87 (
,
SRULB
,
CS0
CS1
CS2
CS3
CSZB
CSZC
CSZD
CSZE
CSZE
,
)
,
,
)
SRUUB
SDCS
CSZA
,
,
,
,
SRULB
SRUUB
WRUL
WRUU
)
,
SDCS
,
,
)
)
ND
ND
TMP92CH21
0
1
)
CE
CE
2009-06-19
)
)