TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 116

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(5) Recovery (Data hold) cycle control
read cycle. Therefore, a data conflict problem may occur. To avoid this problem,
1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to
BmCSH<BmREC> register.
•
•
Some memory is defined by AC specification about data hold time by
This 1-dummy cycle is inserted when the next cycle is for another CS-block.
When no dummy cycle is inserted (0 waits)
When inserting a dummy cycle (0 waits)
A23 to A0
A23 to A0
SDCLK
0
1
SDCLK
CSm
CSn
RD
CSm
CSn
RD
No dummy cycle is inserted (Default).
Dummy cycle is inserted.
<BnREC> (BnCSH register)
92CH21-114
Dummy
TMP92CH21
CE
2009-06-19
or
OE
for