TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 231

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

EPx_SINGLE1
EPx_BCS1
(07D3H)
(07D1H)
3.10.3.25 EPx_SINGLE Register
bit Symbol
Read/Write
Reset State
3.10.3.26 EPx_BCS Register
Reset State
Read/Write
bit Symbol
Note: Endpoint 3 supports only SINGLE mode in the TMP92CH21.
Bit number
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is “1”, EPx_SINGLE bit becomes valid in the following content.
If setting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to “1”.
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write “1” to EPx_BCS bit regardless of whether endpoint is used or not.
If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to “1”.
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
This register sets mode of access to FIFO in each endpoint.
EP3_SELECT EP2_SELECT EP1_SELECT
EP3_SELECT EP2_SELECT EP1_SELECT
R/W
R/W
7
7
0
0
0: DUAL mode
0: Invalid
0: Reserved
0: Invalid
R/W
R/W
6
6
0
0
1: SINGLE mode
1: Valid
1: CPU access
1: Valid
92CH21-229
R/W
R/W
5
5
0
0
4
4
EP3_SINGLE EP2_SINGLE EP1_SINGLE
EP3_BCS
R/W
R/W
3
3
0
0
EP2_BCS
R/W
R/W
2
2
0
0
EP1_BCS
R/W
R/W
1
1
0
0
TMP92CH21
2009-06-19
0
0