TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 158

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

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(b) Sub routine (Bank 0 in LOCAL-Y)
400000H
4000xxH
5000yyH
Address
Logical
No.17 and No.18 are settings for BANK 1 of LOCAL-Y. In this case, LCD display data is
written to SRAM by CPU.
So, (LOCALWY) and (LOCALLY) should be set to the same BANK 1.
No.19 is a setting for BANK 0 of LOCAL-Z to read data from character ROM.
No.20 and No.21 are instructions to read data from character ROM. When CPU outputs
800000H address, this MMU will convert and output 000000H address to external address
bus: A23 to A0. And
the CS2 area at the same time.
These instructions allow the CPU to read data from character ROM.
No.23 is an instruction which changes the program BANK number in the local area. This
setting is disabled.
No.24 and No.25 are instructions to write data to SRAM. When CPU outputs 400000H
address, this MMU will convert and output 200000H address to external address bus: A23
to A0. And
the same time.
These instructions allow the CPU to write data to SRAM.
No.28 and No.29 are settings to set LCD starting address to LCD controller. When LCDC
outputs 400000H address in DMA cycle, this MMU will convert and output 200000H
address to external address bus: A23 to A0. And
its logical address is in the CS1 area at the same time.
These instructions allow the LCDC to read data from SRAM.
No.30 is an instruction to start LCD display operation.
0000xxH
000000H
1000yyH
Physical
Address
CS1
for SRAM will be asserted because its logical address is in the CS1area at
No
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CSZA
org
ld
ld
ld
ld
ld
:
ld
ld
ld
:
:
ld
ld
ld
:
ret
for NOR flash will be asserted because its logical address is in
92CH21-156
Instruction
400000H
(localwy), 81H
(locally), 81H
(localrz), 80H
xiy, 800000H
wa, (xiy)
(localpy), 82H
xix, 400000H
(xix), bc
xiz, 400000H
(lsarcl), xiz
(lcdctl0), 01H
CS1
;
; BANK 1 in LOCAL-Y is set as write data for
; BANK 1 in LOCAL-Y is set as LCD display data
; BANK 0 in LOCAL-Z is set as read data for
; Index address register to read character ROM
; Reading character ROM
; Convert it to display data
;
; Index address register to write LCD
; Writing LCD display data
; Setting LCD controller
;
; Setting LCD start address to LCDC
;
; Start LCD display operation
;
;
LCD display RAM
for LCD display RAM
character ROM
display data
for SRAM will be asserted because
Comment
TMP92CH21
2009-06-19