TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 22

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

SYSCR0
(10E0H)
SYSCR1
(10E1H)
SYSCR2
(10E2H)
3.3.2
Note 1: The unassigned registers, SYSCR0<bit5:3>, SYSCR0<bit1:0>, SYSCR1<bit7:4>, and
Note 2: Low-frequency oscillator is enabled on reset.
Bit symbol
Read/Write
Reset state
Function
Bit symbol
Read/Write
Reset state
Function
Bit symbol
Read/Write
Reset state
Function
SFR
SYSCR2<bit6, bit1:0> are read as undefined value.
High-
frequency
oscillator
(fc)
0: Stop
1: Oscillation
Always
write “0”
XEN
R/W
7
7
7
1
−
0
R/W
Low-
frequency
oscillator
(fs)
0: Stop
1: Oscillation
XTEN
6
6
6
1
Figure 3.3.3 SFR for System Clock
Warm-up timer
00: Reserved
01: 2
10: 2
11: 2
WUPTM1
R/W
5
5
5
1
8
14
16
/input frequency
92CH21-20
/input frequency
/input frequency
WUPTM0
R/W
4
4
4
0
Select
system clock
0: fc
1: fs
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
HALTM1
SYSCK
R/W
R/W
3
3
3
0
1
Select gear value of high-frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
Warm-up
timer
0: Write
1: Write
0: Read
1: Read
HALTM0
GEAR2
don’t care
start
timer
end
warm-up
do not end
warm-up
WUEF
R/W
R/W
2
2
2
0
1
1
GEAR1
R/W
1
1
1
0
TMP92CH21
2009-06-19
GEAR0
0
0
0
0