TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 104

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.5.16
Port L (PL0 to PL7)
PL3 pins output “0”.
or output using the control register PLCR. Resetting resets the control register PLCR to “0”
and sets PL4 to PL7 to input ports. In addition to functioning as a general-purpose I/O port,
port L can also function as a data bus for an LCD controller (LD0 to LD7). The above
settings are made using the function register PLFC.
PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to
PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input
Reset
LD4 to LD7
LD0 to LD3
Direction control
Function control
Function control
Output latch
PL read
PLCR write
PLFC write
PL read
Output latch
PL write
PLFC write
Reset
PL write
S
R
Figure 3.5.43 Register for Port L0 to L3
Figure 3.5.44 Register for Port L4 to L7
92CH21-102
A
B
Selector
Selector
A
B
S
S
Selector
S
B
A
PL0 to PL3 (LD0 to LD3)
PL4 to PL7 (LD4 to LD7)
TMP92CH21
2009-06-19