TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 386

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.16.2
TMP92CH21
Pin Name
A10
A11
A12
A13
A14
A15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Operation Description
(1) Memory access control
(2) Instruction executing on SDRAM
* AP: Auto Precharge
signals ( SDCS , SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM,
SDUUDQM, SDCLK and SDCKE) are operating during the time CPU or LCDC
accesses CS1 or CS2 area.
multiplex width is decided by setting SDACR2<SMUXW0:1> of use memory size. The
relation between multiplex width and Row/Column address is shown in Table 3.16.3.
write. When the LCDC accesses the SDRAM, the burst length is fixed to full page.
registers. In the full page burst read cycle, a mode register set cycle and a precharge
cycle are automatically inserted at the beginning and end of a cycle.
not operate.
1.
2.
<SMUXW> “00”
SDRAM controller is enabled when SDACR1<SMAC> = 1. And then SDRAM control
In the access cycle, outputs row/column address through A0 to A15 pin. And
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single
SDRAM access cycle is shown in Figure 3.16.2 and Figure 3.16.3.
SDRAM access cycle number does not depend on the settings of B1CSL and B2CSL
The CPU can execute instructions on SDRAM. However, the following functions do
These operations must be executed by another memory such as the built-in RAM.
a)
b)
Address multiplex function
TypeA
Burst length
EA24
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A9
Executing HALT instruction
Execute instructions that write to SDCMM register
<SMUXW> “01”
Row Address
Table 3.16.1 Address Multiplex
TypeB
EA24
EA25
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
Address of SDRAM Accessing Cycle
92CH21-384
<SMUXW> “10”
TypeC
EA24
EA25
EA26
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1CSH<BnBUS> = “01”
16-Bit Data Bus Width
AP *
A10
A1
A2
A3
A4
A5
A6
A7
A8
A9
Column Address
Row address
B1CSH<BnBUS> = “10”
32-Bit Data Bus Width
TMP92CH21
2009-06-19
AP *
A10
A11
A2
A3
A4
A5
A6
A7
A8
A9