TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 354

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LD7 to LD0
LD7 to LD0
LD7 to LD0
3.14.3.7 Timing Diagram of LD Bus
LCP0
LCP0
LCP0
f
SYS
Note: If the LCP cycle is too slow it may not transfer correctly.
data will not transfer correctly. t
than t
when the setting is too fast , there will be not enough transmission data in FIFO, and
LCD data will not transfer correctly.
If LCP cycle is not set at a suitable speed with respect to the refresh rate, LD bus
Data transmission must finish in t
The kind of display memory and display mode determine LCP speed. In other words,
WAIT, internal SRAM and external SDRAM: 16, 32, 64, 128, 256 and 512 Mbits.
controlled.
falling edge of LCP0.
LP
The TMP92CH21 can select to display RAM for external SRAM: Available to set
As a 480-byte FIFO buffer is built into this LCDC, the LD bus speed can be
The speed can be selected from 3 kinds of cycle: (f
LD bus data: LD11 to LD0 is out at rising edge of LCP0, LCD driver receives at
time. For setting of SCC, refer to “basic clock setting” of “refresh rate setting”.
t
LP
[s] = (1/f
Figure 3.14.9 Selection of LCP Cycle
SYS
[Hz]) × 16 × (SCC+1)
92CH21-352
LP
time is shown in the equation below.
LP
time. Set SCC clock and LCP0 speed to be less
SYS
CP 2-clock
CP 4-clock
/2, f
SYS
/4, and fSYS/8)
TMP92CH21
CP 8-clock
2009-06-19