TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 402

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.17.3.2 ECC Control
4)
ND0FMCR. This circuit executes ECC data calculation. However, ECC comparison
and error correction is not executed. This must be executed using software.
is 0xD0 (write mode) or 0x50 (read mode). This is 6-byte data, and six NDECCRD read
operations are required. The order of the data is as follows.
The NDFC contains the ECC calculating circuits. The circuits are controlled by
The calculated ECC data can be read from the NDECCRD register when ND0FMCR
ID read
(1) ND0FMCR:
(2) ND0FDTR:
(3) ND0FMCR:
(4) ND0FDTR:
(5) ND0FMCR:
(6) ND0FDTR:
(7) ND0FDTR:
The ID read sequence is as follows.
First data:
Second data:
Third data:
Fourth data:
Fifth data:
Sixth data:
Set 0x1D for NDCLE signal enable and command mode.
Set 0x90 for the ID Read command.
Set 0x00.
Read Maker code.
Read Device code.
Set 0x1E for NDALE signal enable and the address mode.
Set 0x1C for the data mode without ECC calculation.
92CH21-400
LPR [7:0]
LPR [15:8]
CPR [5:0], 2’b11
LPR [23:16]
LPR [31:24]
CPR [11:6], 2’b11
TMP92CH21
2009-06-19