TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 51

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
DMAR
Request
Name
(2) Soft start function
(3) Transfer control registers
DMA
micro DMA soft start function, in which micro DMA is initiated by a write cycle which
writes to the register DMAR.
(If write “0” to each bit, micro DMA doesn’t operate). On completion of the transfer, the
bits of DMAR which support the end channel are automatically cleared to 0.
writing “1”. If read “1”, micro DMA transfer isn’t started yet.
from the initiation of micro DMA until the value in the micro DMA transfer counter is 0.
If execatee soft start during micro DMA transfer by interrupt source, micro DMA
transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid
writign to other bits by mistake.
following registers. An instruction of the form LDC cr, r can be used to set these
registers.
The TMP92CH21 can initiate micro DMA either with an interrupt or by using the
Writing 1 to any bit of the register DMAR causes micro DMA to be performed once.
Only one channel can be set once for DMA request. (Do not write “1” to plural bits.)
When writing again 1 to the DMAR register, check whether the bit is “0” before
When a burst is specified by the DMAB register, data is transferred continuously
The transfer source address and the transfer destination address are set in the
Address
(Prohibit
Channel 0
Channel 7
RMW)
109H
DMAS0
DMAD0
DMAS7
DMAD7
32 bits
DREQ7
DMAC0
DMAC7
16 bits
7
0
DMAM0
DMAM7
8 bits
DREQ6
6
0
92CH21-49
DMA source address register 0
DMA destination address register 0
DMA counter register 0
DMA mode register 0
DMA source address register 7
DMA destination address register 7
DMA counter register 7
DMA mode register 7
DREQ5
5
0
1: DMA request in software
DREQ4
4
0
R/W
DREQ3
3
0
DREQ2
2
0
DREQ1
1
0
TMP92CH21
2009-06-19
DREQ0
0
0