TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 180

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
3.9.4
Output extension
Output extension
TMP92CH21
TMP92CH21
Operation in Each Mode
(1) Mode 0 (I/O interface mode)
data to or receiving data from an external shift register.
SCLK input mode to input external synchronous clock SCLK.
SCLK
SCLK
TXD
TXD
Port
Port
This mode allows an increase in the number of I/O pins available for transmitting
This mode includes the SCLK output mode to output synchronous clock SCLK, and
Figure 3.9.18 Example of SCLK Input Mode Connection
Figure 3.9.17 SCLK Output Mode Connection Example
TC74HC595 or equivalent
TC74HC595 or equivalent
SI
SCK
RCK
SI
SCK
RCK
External clock
Shift register
Shift register
92CH21-178
G
G
C
D
H
C
D
H
A
B
E
A
B
E
F
F
Input extension
Input extension
TMP92CH21
TMP92CH21
SCLK
SCLK
RXD
RXD
Port
Port
TC74HC165 or equivalent
TC74HC165 or equivalent
QH
CLOCK
S/
QH
CLOCK
S/
External clock
Shift register
L
L
Shift register
TMP92CH21
G
G
C
D
H
C
D
H
A
B
E
A
B
E
F
F
2009-06-19

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