TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 379

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

MELALMC
(1331H)
MELFH
(1333H)
ALMINT
(1334H)
ALM
(1330H)
MELFL
(1332H)
3.15.2
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note 1: MELALMC<FC1> is always read “0”.
Note 2: When setting MELALMC register except <FC1:0> while the free-run counter is running, <FC1:0> is kept
Control Registers
“01”.
Free-run counter control
00: Hold
01: Restart
10: Clear and stop
11: Clear and start
0: Stop and
Control
melody
counter
1: Start
MELON
clear
FC1
R/W
AL8
ML7
7
0
7
0
0
0
7
7
7
R/W
FC0
ML6
AL7
6
0
6
0
0
6
6
6
Alarm
waveform
invert
1: Invert
MELALMC Register
ALMINV
ALMINT Register
MELFH Register
write “0”
MELFL Register
Always
R/W
92CH21-377
ALM Register
R/W
ML5
AL6
5
0
5
0
0
5
5
−
0
5
Setting melody frequency (Lower 8 bits)
IALM4E
Setting alarm pattern
ML4
AL5
4
−
0
4
0
0
0
4
4
4
R/W
R/W
1: Interrupt enable for INTALM4 to INTALM0
IALM3E
ML11
ML3
AL4
Always write “0”
3
0
−
0
0
0
0
3
3
3
3
Setting melody frequency (Upper 4 bits)
R/W
IALM2E
ML10
R/W
ML2
AL3
2
0
0
0
−
0
0
2
2
2
2
R/W
IALM1E
ML9
ML1
AL2
1
0
0
0
0
0
1
−
1
1
1
TMP92CH21
2009-06-19
Output
waveform
select
0: Alarm
1: Melody
MELALM
IALM0E
R/W
ML8
ML0
AL1
0
0
0
0
0
0
0
0
0
0