TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 267

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(d-2) Isochronous receiving mode
Control flow
FIFO by OUT token is received to the CPU in the next frame.
X condition or Y condition. The flow below explains X Condition (packet A)
and Y Condition (packet B) in present frame.
1.
2.
3.
4.
5.
Transaction format for Isochronous transfer type in receiving is given below.
Isochronous transfer type is frame management. And data that is written to
Below are two conditions in FIFO of Isochronous receiving mode
X. FIFO for storing data received from host in present frame
Y. FIFO for storing data for transmitting host in previous frame
FIFO that is divided into two (packet A and packet B) conditions is whether
X and Y conditions change one after the other by receiving SOF.
Below is control flow in the UDC when receiving OUT token.
The whole transaction is processed by hardware.
The UDC finishes normally by the above transaction.
The CPU takes back packet A’s data.
Token packet is received and address endpoint number error is confirmed,
and it checks whether the relevant endpoint transfer mode corresponds
with the OUT token. If it does not correspond, the state returns to IDLE.
Condition of status register is confirmed.
Data packet is received.
Data is transferred from SIE into the UDC to packet A’s FIFO (X
Condition).
After last data was transferred, and counted CRC is compared with
transferred CRC. When transfer is finished, the result is reflected to
STATUS. However, data is stored FIFO, data number that packet A is
received is set to DATASIZE register of packet A.
The transaction when SOF token from host is received is given below.
•
•
•
•
•
•
•
•
•
transferring
(DATASET register bit = 0)
(DATASET register bit = 1)
Token: OUT
Data: DATA0
INVALID condition: State returns to IDLE.
Change packet A’s FIFO from X Condition to Y Condition.
Change packet B from Y Condition to X Condition, and clear data.
Prepare for next transfer.
Set frame number to frame register.
Assert SOF and inform externally that frame is incremented.
DATASET register set packet A bit and clear packet B bit
arrangement loading in present frame.
If CRC comparison result agrees, DATAIN is set to STATUS. If result
does not agree, RX_ERR is set to STATUS.
92CH21-265
TMP92CH21
2009-06-19