UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1037

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence,
Caution If a request to change the mode from the initialization mode to any operation mode is made to
Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-
clear all the TRQ bits.
execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive
error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11
contiguous recessive bits 128 times on the bus again.
Figure 20-55. Bus-off Recovery (Normal Operation Mode with ABT)
shot mode, self-test mode
No
Access to register other
C0GMCTRL registers.
Clear ABTTRG bit = 1
Set C0CTRL register.
Set C0CTRL register.
(Clear OPMODE bit.)
Set ABTTRG bit = 0
Clear all TRQ bit
(Set OPMODE bit.)
than C0CTRL and
Set CCERC bit = 1
Clear ABTTRG bit.
Forced recovery
Set CCERC bit.
BOFF bit = 1?
from bus off?
START
END
Yes
Yes
Note
No
Set C0CTRL register.
(Set OPMODE.)
Wait for recovery
from bus off.
CHAPTER 20 CAN CONTROLLER
Page 1037 of 1509