UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 722

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) UARTCn control register 0 (UCnCTL0)
(2) UARTCn control register 1 (UCnCTL1)
(3) UARTCn control register 2 (UCnCTL2)
(4) UARTCn option control register 0 (UCnOPT0)
(5) UARTCn option control register 1 (UCnOPT1)
(6) UARTCn status register (UCnSTR)
(7) UARTCn receive shift register
(8) UARTCn receive data register (UCnRX)
(9) UARTCn transmit shift register
(10) UARTCn transmit data register (UCnTX)
The UCnCTL0 register is an 8-bit register used to specify the UARTCn operation.
The UCnCTL1 register is an 8-bit register used to select the input clock for the UARTCn.
The UCnCTL2 register is an 8-bit register used to control the baud rate for the UARTCn.
The UCnOPT0 register is an 8-bit register used to control serial transfer for the UARTCn.
The UCnOPT1 register is an 8-bit register used to control 9-bit length serial transfer for the UARTCn.
The UCnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one of
the reception error flags is set (to 1) upon occurrence of a reception error.
This is a shift register used to convert the serial data input to the RXDCn pin into parallel data. Upon reception of 1
byte of data and detection of the stop bit, the receive data is transferred to the UCnRX register.
This register cannot be manipulated directly.
The UCnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in the
most significant bit (when data is received with the LSB first).
In the reception enabled status, receive data is transferred from the UARTCn receive shift register to the UCnRX
register in synchronization with the completion of shift-in processing of 1 frame.
Transfer to the UCnRX register also causes the reception completion interrupt request signal (INTUCnR) to be
output.
The transmit shift register is a shift register used to convert the parallel data transferred from the UCnTX register
into serial data.
When 1 byte of data is transferred from the UCnTX register, the shift register data is output from the TXDCn pin.
This register cannot be manipulated directly.
The UCnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UCnTX
register. When data can be written to the UCnTX register (when data of one frame is transferred from the UCnTX
register to the UARTCn transmit shift register), the transmission enable interrupt request signal (INTUCnT) is
generated.
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
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