UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 99

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(3) Restriction on conflict between sld instruction and interrupt request
(a) Description
(b) Countermeasure
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction
following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution
result of the instruction in <1> may not be stored in a register.
Instruction <1>
Instruction <2>
<Example>
<i> ld.w [r11], r10
<ii> mov r10, r28
<iii> sld.w 0x28, r10
<1> When compiler (CA850) is used
<2> For assembler
• ld instruction:
• sld instruction:
• Multiplication instruction: mul, mulh, mulhi, mulu
• Insert a nop instruction immediately before the sld instruction.
• Do not use the same register as the sld instruction destination register in the above instruction <ii>
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
When executing the sld instruction immediately after instruction <ii>, avoid the above operation using
either of the following methods.
executed immediately before the sld instruction.
•
•
•
mov
reg2
satadd reg1,
reg2
and
reg2
add
reg2
mulh
reg2
reg1,
reg1,
reg1,
reg1,
If the decode operation of the mov instruction <ii> immediately before the sld
instruction <iii> and an interrupt request conflict before execution of the ld instruction
<i> is complete, the execution result of instruction <i> may not be stored in a register.
ld.b, ld.h, ld.w, ld.bu, ld.hu
sld.b, sld.h, sld.w, sld.bu, sld.hu
not
reg2
satadd imm5,
reg2
tst reg1, reg2
add
reg2
shr
reg2
imm5,
imm5,
reg1,
satsubr reg1,
reg2
or reg1, reg2
subr
reg2
cmp
reg2
sar
reg2
imm5,
reg1,
reg1,
CHAPTER 3 CPU FUNCTION
satsub
reg2
xor
reg2
sub
reg2
cmp
reg2
shl
reg2
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imm5,
imm5,
reg1,
reg1,
reg1,