UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1295

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0)
Note V850ES/JH3-H only
Remark
The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI
pin via bit 2 and the external interrupt pins (INTP00 to INTP04) via bits 0, 1, 3 to 5.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the port
Caution Be sure to set the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI or
Remark
INTF0n
For how to specify a valid edge, see Table 23-5.
function, an edge may be detected. Therefore, set the INTF0n and INTR0n bits to 00, and then set
the port mode.
INTP00 to INTP04 pins.
n = 0, 1:
n = 2:
n = 3 to 5: Control of INTP02 to INTP04 pins
INTR0
0
0
1
1
INTF0
After reset: 00H
Control of INTP00 and INTP01 pins
Control of NMI pin
INTR0n
7
0
7
0
0
1
0
1
R/W
6
0
6
0
Table 23-5. Valid Edge Specification
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
No edge detected
Rising edge
Falling edge
Both rising and falling edges
Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H
INTR05
INTF05
INTP04
INTP04
5
5
INTP03
INTR04
INTP03
INTF04
4
4
Valid Edge Specification (n = 0 to 5)
INTP02
INTR03
INTP02
INTF03
3
3
INTF02
INTR02 INTR01
NMI
NMI
2
2
INTF01
INTP01
INTP01
1
1
Note
Note
INTR00
INTF00
INTP00
INTP00
0
0
Note
Note
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