UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 448

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(7) TMT0 I/O control register 3 (TT0IOC3)
The TT0IOC3 register is an 8-bit register that controls the encoder clear function operation.
The TT0IOC3 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TT0IOC3
After reset: 00H
TT0SCE
• Clears the 16-bit counter to 0000H when the valid edge of TECR0 pin specified by
• Clears the 16-bit counter to 0000H when the clear level conditions of the TT0ZCL,
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is valid and that of the
• Setting of the TT0ZCL, TT0BCL, and TT0ACL bits is invalid and setting of
• Be sure to set the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits to 10 or 11
Setting of the
Setting of the
Setting of the
TT0SCE
TT0BCL
TT0ACL
TT0ZCL
the TT0ECS1 and TT0ECS0 bits is detected when the TT0SCE bit = 0.
TT0BCL, and TT0ACL bits match the input levels of the TECR0, TENC01, and
TENC00 pins when TT0SCE bit = 1.
TT0ECS1 and TT0ECS0 bits is invalid when the TT0SCE bit = 1.
An encoder clear interrupt request signal (INTTTI0EC) is not generated.
the TT0ECS1 and TT0ECS0 bits is valid when the TT0SCE bit = 0.
The INTTTI0EC signal is generated when the valid edge specified by the TT0ECS1
and TT0ECS0 bits is detected.
when the TT0SCE bit = 1.
Operation is not guaranteed if the TT0UDS1 and TT0UDS0 bits = 00 or 01 and
the TT0SCE bit = 1.
0
1
0
1
0
1
0
1
7
R/W
TT0ZCL
Clears 16-bit counter on detection of edge of encoder clear signal (TECR0 pin).
Clears 16-bit counter on detection of clear level condition of the TENC00,
TENC01, and TECR0 pins.
Clears low level of the TECR0
Clears high level of the TECR0
Clears low level of the
Clears high level of the
Clears low level of the
Clears high level of the
TT0ZCL
TT0BCL
TT0ACL
6
Address: FFFFF606H
Clear level selection of encoder input signal (TENC01 pin)
Clear level selection of encoder input signal (TENC00 pin)
Clear level selection of encoder clear signal (TECR0 pin)
TT0BCL TT0ACL TT0ECS1 TT0ECS0 TT0EIS1 TT0EIS0
bit is valid only when the
bit is valid only when the
bit is valid only when the
5
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TENC01 pin.
TENC00 pin.
TENC01 pin.
TENC00 pin.
Encoder clear selection
4
pin.
pin.
3
TT0SCE
TT0SCE
TT0SCE
bit = 1.
bit = 1.
bit = 1.
2
1
0
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