UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1394

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
32.2 Debugging Without Using DCU
and TXDC0), pins for CSIF0 (SIF0, SOF0, SCKF0, and HS (P913)), or pins for CSIF3 (SIF3, SOF3, SCKF3, and HS
(P913)) as debug interfaces, without using the DCU.
32.2.1 Circuit connection examples
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
The following describes how to implement an on-chip debug function using MINICUBE2 with pins for UARTC0 (RXDC0
Notes 1.
Remark
Figure 32-3. Circuit Connection Example When UARTC0/CSIF0/CSIF3 Is Used for Communication Interface
2. This pin may be used to supply a clock from MINICUBE2 during flash memory programming. For
3. Because this pin is an (unused) input during debugging, its alternate function can be used. Note that,
4. This connection is designed assuming that the RESET signal is output from the N-ch open-drain
5. The circuit enclosed by a dashed line is designed for flash self programming, which controls the
details, refer to CHAPTER 31 FLASH MEMORY.
within MINICUBE2, a 100 kΩ pull-down resistor is connected.
buffer (output resistance: 100 Ω or less).
FLMD0 pin via ports. Use the port for inputting or outputting the high level. When flash self
programming is not performed, a pull-down resistance for the FLMD0 pin can be within 1 to 10 kΩ.
Refer to Table 32-3 for pins used when UARTC0, CSIF0, or CSIF3 is used for communication interface.
Connect TXDC0/SOF0/SOF3 (transmit side) of the V850ES/JG3-H or V850ES/JH3-H to RXD/SI
(receive side) of the target connector, and TXD/SO (transmit side) of the target connector to
RXDC0/SIF0/SIF3 (receive side) of the V850ES/JG3-H or V850ES/JH3-H.
RESET_IN
RESET_OUT
QB-MINI2
TXD/SO
RXD/SI
FLMD1
FLMD0
CLK
GND
VDD
SCK
Note 1
Note 1
Note 2
Note 3
Note 3
Note 4
HS
V
DD
10 kΩ
1 to 10 kΩ
1 to 10 kΩ
1 to 10 kΩ
V
V
DD
DD
1 kΩ
V
DD
3 to 10 kΩ
1 to 10 kΩ
CHAPTER 32 ON-CHIP DEBUG FUNCTION
10 kΩ
RESET signal
V
DD
100 Ω
V850ES/JG3-H, V850ES/JH3-H
V
V
RESET
TXDC0/SOF0/SOF3
RXDC0/SIF0/SIF3
SCKF0/SCKF3
HS (P913)
FLMD1
FLMD0
Port X
DD
SS
Reset circuit
Note 5
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