UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 241

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
with the count clock, and the counter starts counting. At this time, the output of the TOAAn0 pin is inverted. Additionally,
the set value of the TAAnCCR0 register is transferred to the CCR0 buffer register.
to 0000H, the output of the TOAAn0 pin is inverted, and a compare match interrupt request signal (INTTAAnCC0) is
generated.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TAAnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The interval can be calculated by the following expression.
Interval = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Remark
TAAnCTL1
TAAnCTL0
Note This bit can be set to 1 only when the interrupt request signals (INTTAAmCC0 and INTTAAmCC1)
Remark m = 0 to 3, 5
(a) TAAn control register 0 (TAAnCTL0)
(b) TAAn control register 1 (TAAnCTL1)
are masked by the interrupt mask flags (TAAmCCMK0 and TAAmCCMK1) and timer output
(TOAAm1) is performed. However, set the TAAmCCR0 and TAAmCCR1 registers to the same value
(see 7.5.1 (2) (d) Operation of TAAnCCR1 register).
m = 0 to 3, 5
n = 0 to 5
n = 0 to 5
TAAnCE
0/1
0
Figure 7-9. Register Settings for Interval Timer Mode Operation (1/2)
TAmEST
0
0
TAAmEEE
0/1
0
Note
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
0
TAAnMD2 TAAnMD1 TAAnMD0
TAAnCKS2 TAAnCKS1 TAAnCKS0
0/1
0
0/1
0
0/1
0
0, 0, 0:
Interval timer mode
0: Operates on count clock
1: Counts with external
Select count clock
0: Stops counting
1: Enables counting
selected by TAAmCKS0
to TAAmCKS2 bits
event count input signal
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