UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 535

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
detected, the count value of the 16-bit counter is stored in the TT0CCRn register, the 16-bit counter is cleared to 0000H,
and a capture interrupt request signal (INTTT0CCn) is generated.
request signal (INTTT0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing
the CLR instruction via software.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is later
The pulse width is calculated as follows.
If the valid edge is not input to the TIT0n pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × TT0OVF bit set (1) count + Captured value) × Count clock cycle
INTTT0CCn signal
TT0CCRn register
n = 0, 1
Remark
INTTT0OV signal
TIT0n pin input
16-bit counter
TT0OVF bit
TT0CE bit
FFFFH
0000H
n = 0, 1
Figure 9-40. Basic Timing in Pulse Width Measurement Mode
0000H
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
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D
3