UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 275

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
External trigger input
INTTAAnCC0 signal
INTTAAnCC1 signal
(only when software
TAAnCCR0 register
TAAnCCR1 register
(a) Note on rewriting TAAnCCRm register
TOAAn0 pin output
TOAAn1 pin output
(TIAAn0 pin input)
trigger is used)
To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
When the TAAnCCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOAAn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark
16-bit counter
00
TAAnCE bit
> D
FFFFH
01
0000H
01
and less than D
and D
n = 0 to 3, 5
m = 0, 1
11
10
and less than D
> D
11
, if the TAAnCCR1 register is rewritten when the count value of the 16-bit counter is
00
, each set value is reflected as soon as the register has been rewritten and
Delay
(D
D
10
10
)
10
Active level width
(D
11
00
and if the TAAnCCR0 register is rewritten when the count value is greater
, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1
D
− D
00
10
01
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
+ 1)
D
, the counter generates the INTTAAnCC0 signal, deasserts the
10
D
00
Delay
(D
00
D
10
to D
10
)
Active level width
(D
00
D
01
− D
00
and the TAAnCCR1 register from D
10
+ 1)
D
Delay
(10000H + D
10
D
00
11
)
Active level width
(D
D
D
D
11
01
11
01
D
− D
01
Page 275 of 1509
11
10
+ 1)
to D
11
where