UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 336

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) TABn control register 1 (TABnCTL1)
The TABnCTL1 register is an 8-bit register that controls the operation of TABn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TABnCTL1
(n = 0, 1)
After reset: 00H
Cautions 1. The TABnEST bit is valid only in the external trigger pulse output mode or
TABnMD2
TABnEST
TABnEEE
The TABnEEE bit selects whether counting is performed with the internal count
clock or the valid edge of the external event count input.
0
1
0
1
0
0
0
0
1
1
1
1
0
7
2. Be sure to set bits 3, 4, and 7 to “0”.
3. External event count input is selected in the external event count mode
4. Set
one-shot pulse output mode. In any other mode, writing 1 to this bit is
ignored.
regardless of the value of the TABnEEE bit.
TABnCTL0.TABnCE bit = 0. (The same value can be written when the
TABnCE bit = 1.)
performed with the TABnCE bit = 1.
performed, clear the TABnCE bit to 0 and then set the bits again.
Generate a valid signal for external trigger input.
• In one-shot pulse output mode: A one-shot pulse is output with writing
• In external trigger pulse output mode: A PWM waveform is output with
Disable operation with external event count input.
(Perform counting with the count clock selected by the
TABnCTL0.TABnCK0 to TABnCTL0.TABnCK2 bits.)
TABnMD1
TABnEST TABnEEE
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
R/W
6
0
0
1
1
0
0
1
1
the
Address: TAB0CTL1 FFFFF541H, TAB1CTL1 FFFFF561H
TABnMD0
TABnEEE
5
0
1
0
1
0
1
0
1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Triangular wave PWM mode
The operation is not guaranteed when rewriting is
4
0
Software trigger control
and
Count clock selection
TABnMD2
1 to the TABnEST bit as the trigger.
3
0
−
Timer mode selection
writing 1 to the TABnEST bit as
the trigger.
TABnMD2 TABnMD1 TABnMD0
2
to
If rewriting was mistakenly
TABnMD0
1
bits
0
when
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the