UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 808

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
18.6.14 Clock timing
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Notes 1. The INTCFnT interrupt is set when the data written to the CFnTX register is transferred to the data
Caution In single transfer mode, writing to the CFnTX register with the CFnTSF bit set to 1 is ignored.
Remark
2. The INTCFnR interrupt occurs if reception is correctly ended and receive data is ready in the CFnRX
SIFn capture
SCKFn pin
SOFn pin
Reg-R/W
INTCFnT
interrupt
INTCFnR
interrupt
CFnTSF bit
SCKFn pin
SIFn capture
SOFn pin
Reg-R/W
INTCFnT
interrupt
INTCFnR
interrupt
CFnTSF bit
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCFnT interrupt request signal is
not generated, but the INTCFnR interrupt request signal is generated upon end of communication.
register while reception is enabled. In the single mode, the INTCFnR interrupt request signal is
generated even in the transmission mode, upon end of communication.
This has no effect on the operation during transfer.
For example, if the next data is written to the CFnTX register when DMA is started by
generating the INTCFnR signal, the written data is not transferred because the CFnTSF bit is
set to 1.
Use the continuous transfer mode, not the single transfer mode, for such applications.
n = 0 to 4
Note 1
Note 2
Note 1
Note 2
(ii) Communication type 3 (CFnCKP and CFnDAP bits = 10)
(i) Communication type 1 (CFnCKP and CFnDAP bits = 00)
D7
D7
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
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