UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 807

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
18.6.13 Reception error
reception completion interrupt request signal (INTCFnR) is generated again when the next receive operation is completed
before the CFnRX register is read after the INTCFnR signal is generated, and the overrun error flag (CFnSTR.CFnOVE) is
set to 1.
reception error has occurred, the INTCFnR signal is generated again upon the next reception completion if the CFnRX
register is not read.
next receive data from the INTCFnR signal generation.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
When transfer is performed with reception enabled (CFnCTL0.CFnRXE bit = 1) in the continuous transfer mode, the
Even if an overrun error has occurred, the previous receive data is lost since the CFnRX register is updated. Even if a
To avoid an overrun error, complete reading the CFnRX register by one half clock before sampling the last bit of the
(1) Operation timing
SIFn pin capture
INTCFnR signal
CFnRX register
CFnRX register
Shift register
CFnOVE bit
read signal
SCKFn pin
SIFn pin
(1) Start continuous transfer.
(2) Completion of the first transfer
(3) The CFnRX register cannot be read until one half clock before the completion of the second transfer.
(4) An overrun error occurs, and the reception completion interrupt request signal (INTCFnR) is
Remark
timing
generated, and then the overrun error flag (CFnSTR.CFnOVE) is set to 1.
overwritten.
n = 0 to 4
(1)
01H
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
(2)
AAH
(3)
(4)
The receive data is
55H
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