UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1340

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(1) Operation when main clock oscillation is stopped (CLME bit = 1)
(2) Clock monitor status after RESET input
Clock monitor status
Internal oscillation
Internal oscillation
RESF.CLMRF bit
(CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in
Figure 27-2.
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1 by
software at the end of the oscillation stabilization time of the main clock, monitoring is started.
CLM.CLME bit
CPU operation
Internal reset
Main clock
Main clock
RESET
signal
CLME
clock
clock
Figure 27-2. Reset Period Due to That Oscillation of Main Clock Is Stopped
Monitoring
operation
Normal
Figure 27-3. Clock Monitor Status After RESET Input
Reset
stabilization time
Four internal oscillation clocks
Clock supply
Oscillation
stopped
Monitoring stopped
CHAPTER 27 CLOCK MONITOR
Normal operation
Set to 1 by software
Monitoring
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